The present invention relates to a circuit for detection of any position difference of output data due to erroneous data written into a memory.
Along with the development of data processing systems, the memories used therein have tremendously grown in capacity. In this connection, there have been proposed various error checking apparatuses intended to increase the reliability of memories. Known such error checking apparatus include the error correction and detection circuit described in U.S. Pat. No. 4,296,494, which uses an error correcting code such as the Hamming code, and the memory readback check apparatus, described in U.S. Pat. No. 4,363,125, which compares data having come through the memory and the original data. These prior art apparatus are applicable to random-access memories which require addressing and therefore have terminals for address inputting and address updating (increment). The errors in this type of memory are generally limited to bit inversions in data due to a memory cell failure or some other external factor such as noise. This is because the noise induces to take in the data into the same location of the memory unless the address is updated or a new address is given.
On the other hand, some sequential-access memories need no such addressing. For instance TMS4C1050NL, supplied by Texas Instruments Inc., dispenses with such addressing by the combined use of each write clock pulse and each read clock pulse with an address updating clock pulse. As the write or read address in this kind of memory is updated every time data are written or read, there arises the problem that, once noise or any such external factor works on some, but not all, of a plurality of memory blocks connected in parallel in a memory system, data positions in the affected memory blocks are different from the corresponding data positions in the other memory blocks. No remedy, however, has been taken again such position difference of data in memory blocks.